Nanowire-type channel transistors (nanowire transistors) that can restrain short-channel effects, instead of conventional planar transistors, are now expected to serve as structures for realizing hyperfine MOSFETs of 30 nm or less in gate length. Such a nanowire transistor includes: a silicon substrate; a buried oxide layer formed on the silicon substrate; a semiconductor layer formed on the buried oxide layer, the semiconductor layer including one or more plate-like nanowire made of silicon, the nanowire being to be a channel region; a gate insulating film formed on the side faces and upper face of the nanowire; a gate electrode formed on the gate insulating film; gate sidewalls formed on both sides (in the gate length direction) of the gate electrode; and a source region and a drain region formed in wider portions of the nanowire and the semiconductor layer, with the channel region being interposed between the source region and the drain region. In the nanowire, the region having the gate electrode thereon functions as the channel region. The channel region has a plate-like structure that is approximately 3 to 25 nm in width (length in the gate width direction), and approximately 3 to 40 nm in height. Since the channel region is covered with the gate electrode, the gate electrode has strong control over the channel region, and restrains short-channel effects. A nanowire transistor is also called a tri-gate transistor, as the upper face and both side faces, a total of three faces, of the nanowire function as the channel.
In a nanowire transistor structure, the parasitic resistance of the source/drain portions is higher than that of a planar transistor, and the on-state current is smaller than that of a planar transistor. As a technique to lower the parasitic resistance, epitaxially growing the source/drain portions is effective. By doing so, the heights and widths of the source/drain portions formed on the burled oxide layer are increased through epitaxial growth, and accordingly, the parasitic resistance is lowered. However, the portion surrounded by the gate sidewalls is not epitaxially grown, and the height and width of such a portion remain small. As a result, the portion surrounded by the gate sidewalls becomes a parasitic-resistance bottleneck region, resulting in a high parasitic resistance.
To solve this problem, the bottleneck region located below the sidewalls can be made shorter by using thin sidewalls, and the parasitic resistance can be lowered, according to a report. However, the portion located below the sidewalls still remains a bottleneck region with a high parasitic resistance. Also, the distances between the gate and the epitaxially-grown source/drain portions become shorter. Therefore, the parasitic capacitance becomes larger, resulting in performance degradation. That is, where the sidewalls are made thinner, the parasitic resistance can be lowered, but the parasitic capacitance increases. Where the sidewalls are made thicker, the parasitic capacitance can be reduced, but the parasitic resistance becomes higher. As described above, there is a trade-off relationship between the parasitic capacitance and the parasitic resistance.